The present invention relates generally to designing electronic circuits such as integrated circuits, and more particularly to routing signal paths for electronic circuits.
Modern integrated circuits often have millions of circuit elements such as gates, latches, and drivers in addition to scores of I/O pins. Each of these circuit elements must be electrically connected to other circuit elements, or to I/O pins, via wires (a.k.a. traces). The process of determining the connection path for the circuit wires is referred to as routing.
Circuit timing is dependent on the length and path of the selected route for each wire. Consequently, circuit timing must be considered when routing a circuit. An initial timing analysis for an un-routed circuit may assume an optimal routing such as a ‘Steiner’ routing for each path in the circuit based on horizontal and vertical channels. The timing analysis may compute a slack for each path in the circuit that is the difference of a desired arrival time (which may include a timing margin) and the estimated arrival time. A positive slack implies that the arrival time at a node can be increased without affecting the overall delay of the circuit. Conversely, a negative slack implies that a signal path is too slow, and the signal path must be sped up.